file1:

module pic_wrapper #(
        parameter  ROM_HEX = "x"
) (
        input clk,
        input reset,

        //I/O for the PIC
        input [15:0] gpio_in,
        output [15:0] gpio_out,

        //I/O for the master
        input [15:0] address,
        input [31:0] data_in,
        output reg [31:0] data_out,
        input wen,
        input ren,
        output ready
);

//verilog

endmodule;

--------8<--------------------
file2:

       pic_wrapper #(
                .ROM_HEX("pic/rom_initial.hex")
        ) pic (
                .clk(clk),
                .reset(rst),
                .gpio_in(pic_led),
                .gpio_out(led),
                .address(mem_addr),
                .data_in(mem_wdata),
                .data_out(pic_rdata),
                .wen(pic_select && mem_wstrb==4'b1111),
                .ren(pic_select && mem_wstrb==4'b0000),
                .ready(pic_ready)
        );